1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor nonvolatile memory, and more particularly to the inter-layer dielectric film QC (quality control), inter-layer dielectric screening, and manufacturing methods for a nonvolatile semiconductor memory whose memory cell has a double-layer gate structure comprising a floating gate and control gate.
2. Description of Related Art
The nonvolatile semiconductor memory controls the amount of electrical charge stored in a floating-gate electrode by injecting/emitting electrons via a tunnel oxide. If, for some reason, electrons leave the floating-gate electrode, positioning the threshold value distribution outside a predetermined range, the affected product is judged to be defective. This defect is called a retention failure. FIG. 11 shows a cross-sectional view of the nonvolatile semiconductor memory. Electrons leave via either a tunnel oxide 2 or an inter-layer dielectric 5 that is accumulated between a floating-gate electrode 4 and control-gate electrode 6. The retention failure can be roughly divided into two types: initial failure and failure after a rewrite. As shown in FIG. 12, simple capacitors are usually formed in scribe areas or other different positions on the same wafer used for chip manufacture. The simple capacitors formed in this manner make it possible to evaluate the tunnel oxide and inter-layer dielectric separately. As regards an initial failure, a breakdown voltage test is conventionally conducted to measure the gate oxide breakdown voltage Vg when the capacitors are formed or when all processes are completed. When the breakdown voltage measured in the breakdown voltage testing is higher than the reference breakdown voltage Vgref1, the subsequent processes (chip cutting, plastic molding, and screening) are performed to initiate product shipment. The breakdown voltage is measured at one or more locations. If the breakdown voltage is not measured at all locations, it is measured, for instance, at some nonadjacent upper/lower/left/right locations (A, B, C, D, and E in FIG. 12). The number of measurements to be taken is not limited.
The flowchart in FIG. 13 describes a conventional QC method (quality control method) for a tunnel oxide and inter-layer dielectric. After a wafer passes an initial failure inspection, it is sliced into chips and then sealed into a package. FIG. 14 schematically shows the result of an electrical charge retention test conducted with a manufactured chip. In this test, the same rewrite stress as for an actual operation is applied to a packaged manufactured chip to temporarily emit electrons from the floating-gate electrode, electrons are then injected again from the substrate into the floating-gate electrode until a certain threshold value is reached, and the phenomenon during which electrons left the floating-gate electrode is observed. For acceleration of this phenomenon, the testing setup may occasionally be left at a high temperature. When the chip under test is normal, the threshold value distribution either suffers nonrotational displacement or remains virtually still. However, actual products have a large number of memories. Therefore, they turn out to be defective due to a threshold voltage drop even when a large number of electrons leave a limited number of cells for some reason or other.
Although the testing/evaluation methods for measuring the threshold voltage of a nonvolatile semiconductor memory were disclosed by JP-A No. 35500/1997, which was laid open on Feb. 7, 1997, and JP-A No. 320299/1997, which was laid open on Feb. 12, 1997, these inventions both evaluated the tunnel oxide film quality.
For capacitor-based measurements, there was no conventional quantitative guide for linking a tail bit-failure to a dielectric strength decrease, and no retention test was conducted on a product level after a rewrite operation was performed a number of times stated in the warranty. Further, the cost depended on the yield prevailing after packaging of sliced chips. As regards initial failures, therefore, a nondetectable nonequilibrium tail bit-failure particularly defeated the attempt to reduce the cost.
Accordingly, the object of the present invention is to provide a method of manufacturing a semiconductor device carrying a nonvolatile semiconductor memory through a process that rapidly and easily selects products exhibiting long-term reliability of inter-layer dielectrics while conducting an inspection with a single memory cell or memory array formed in a scribe area without stressing any memory cell.
For nonvolatile semiconductor memories, scaling of a tunnel oxide (2 in FIG. 11) and inter-layer dielectric (5 in FIG. 11) or the increase in the operating voltage is particularly effective for raising the write speed. It is therefore important to immediately solve reliability problems that arise as a secondary effect. Under these circumstances, the inventors studied cases where inter-layer dielectric scaling and operating voltage increase were effected. In consideration of tunnel injection from a substrate, FIG. 16 shows the relationship among inter-layer dielectric field strength, tunnel oxide film thickness, and inter-layer dielectric film thickness. As preconditions, the memory gate length and width, the voltage applied to the control-gate electrode (A in FIG. 16), the memory intrinsic threshold voltage, and the memory threshold voltage were rendered constant. If, for instance, the tunnel oxide film thickness is 10 nm, the inter-layer dielectric field strength is 6.3 MV/cm when the inter-layer dielectric film thickness is 15.5 nm. However, when scaling is conducted to reduce the inter-layer dielectric film thickness to 12.5 nm, the inter-layer dielectric field strength increases to 7.3 MV/cm. Even when tunnel oxide film thickness scaling is conducted, the same result is obtained as in the case of inter-layer dielectric scaling. For inter-layer dielectric film thickness scaling, therefore, it is obvious that the guide for the permissible inter-layer dielectric field strength is important from the viewpoint of reliability. As regards the voltage to be applied to the control-gate electrode, B in FIG. 16 shows the result of a study that was conducted on a case where the voltage was raised by 1 V for operating speed increase when the tunnel oxide film thickness was 8.5 nm. The result indicates that the inter-layer dielectric field strength was increased by about 0.25 mV/cm no matter what the inter-layer dielectric film thickness was.
FIG. 17 shows the result of a study that was conducted to determine the relationship among inter-layer dielectric field strength (absolute value), tunnel oxide film thickness, and inter-layer dielectric film thickness in cases where a tunnel current was used to emit electrons from the floating-gate electrode to the substrate. As the preconditions, the memory gate length and width, the voltage applied to the control-gate electrode (A in FIG. 17), the memory intrinsic threshold voltage, and the memory threshold voltage prevailing after electron emission were rendered constant. The voltage applied to the control-gate electrode was lowered by 1 V for analysis. The result of the analysis is indicated by B in FIG. 17. Even in situations where the threshold voltage was set to a fixed value smaller than the intrinsic threshold voltage value, it was found that scaling of the tunnel oxide and inter-layer dielectric increased the inter-layer dielectric field strength when electrons were emitted from the control-gate electrode. The above findings indicate that tunnel oxide/inter-layer dielectric scaling and operating voltage increase tend to increase the inter-layer dielectric field strength. It is therefore obvious that inter-layer dielectric film quality assurance is an important task to be carried out from now on.
The evaluation method based on the correlation between the threshold voltage (hereinafter referred to as the saturated threshold voltage), which is observed when the electron injection IFTO from substrate (FIG. 19) and the current leakage IONON from floating gate to inter-layer dielectric are balanced, and the threshold voltage decrease after retention in a saturated state is incorporated into a method of manufacturing a nonvolatile semiconductor memory. In other words, after determination of circuitry, device structure, and process, a wafer based on the process is manufactured, and then the critical threshold voltage for screening is determined in accordance with the saturated threshold voltage characteristic derived from electron injection/emission and the threshold voltage decrease after retention of predetermined duration (FIG. 4). Subsequently, the saturated threshold voltage of each wafer is measured. Wafers whose measurements are greater than the critical threshold voltage for screening are removed from the production line. The remaining wafers are subjected to a probe inspection process, chip cutting process, and plastic molding process to sort out nondefective articles for semiconductor device manufacturing purposes (FIG. 5).
The evaluation method is detailed below, beginning with its physical phenomena. In a nonvolatile semiconductor memory, electrons are accumulated at the floating-gate electrode by means of tunnel injection from substrate. The larger the amount of electrical charge accumulated in the floating-gate electrode, the higher the memory threshold voltage. On the other hand, if a positive voltage is applied to the control electrode, the amount of electrical charge in the floating-gate electrode increases and the electric field applied to the inter-layer dielectric increases in strength. Therefore, the threshold voltage increases and the inter-layer dielectric leak current becomes insignificant. When the tunnel current injected into the floating-gate electrode via the tunnel oxide and the leakage into the control-gate electrode via the inter-layer dielectric are balanced, the memory threshold voltage reaches a certain saturation value (saturated threshold voltage). The saturated threshold voltage varies with the degree of inter-layer dielectric leakage. Therefore, the degree of inter-layer dielectric leakage can be discussed by noting the changes in the saturated threshold voltage while the write (erase) conditions are fixed. FIG. 18 shows the result of the analysis of inter-layer dielectric leak current and inter-layer dielectric field strength, which was conducted to study the relationship between the changes in the saturated threshold voltage and the degree of inter-layer dielectric leakage. This analysis was made on the basis of the fact that the tunnel current is equal to the inter-layer dielectric current when the saturated threshold voltage is obtained. The result of this study indicates that an increase in the absolute value of the voltage applied to the control-gate electrode causes an increase in the inter-layer dielectric leak current when the saturated threshold voltage is constant, and that an increase in the saturated threshold voltage causes a decrease in the inter-layer dielectric leak current when the applied voltage is constant. Therefore, the degree of inter-layer dielectric leakage can be monitored by observing how the memory threshold voltage changes upon pulse application while the applied voltage is maintained constant. More specifically, it is possible to conclude that no defect results from inter-layer dielectric leakage when the saturated threshold voltage is higher than a certain level.
Although the above explanation is based on an example in which a write operation is performed by means of injection from substrate, it goes without saying that the same method can also be applied in cases where an erase operation is performed by means of injection from substrate.
Although the above explanation is based on an example in which an operation is performed to achieve injection from substrate, the same method is also applicable to cases where an operation is performed to achieve emission from the floating gate to the substrate. More specifically, if a negative high voltage is applied to the control-gate electrode when electrons are transferred from the floating-gate electrode to the substrate, the memory threshold voltage decreases in a negative direction from its intrinsic threshold level (threshold voltage stabilized by adequate ultraviolet radiation). As a result, the lower the threshold voltage, the greater the inter-layer dielectric field strength. In this type of operation, due attention needs to be paid to the inter-layer dielectric field to be applied at the time of electron emission. It is therefore possible to conclude that the degree of inter-layer dielectric leakage is small if the prevailing memory threshold voltage is increased in a negative direction from its intrinsic threshold level while the voltage applied to the control-gate electrode and the duration of pulse application are maintained constant.
Other and further objects, features and advantages of the invention will appear more fully from the following description.